High-speed links, such as 100 Gbps Ethernet links for example, may have wide data paths. These data paths may be internal to an IC. Conventionally, these data paths may be broken into multiple segments, namely data lanes. Such parsing of data paths may be a design's choice and/or may be to comply with a specification. For example, the IEEE 802.3ba-2010 standard specifies that 100 Gbps Ethernet have 20 logical lanes. For this or other protocol reasons, such multiple lanes may take separate physical paths within an IC, and two or more of such lanes may be combined, for example at an input/output (“I/O”) interface. For example, for an IC with multiple serial transceivers and multiple clock domains, such multiple lanes may cross one or more of such clock domains. Although a design may attempt to keep all lanes aligned, namely so that all data on a data path encounters equivalent delay, use of first-in, first-out buffers (“FIFOs”) to cross clock domain boundaries inherently adds some delay uncertainty for each lane and therefore lane-to-lane latency variation.
Reduction of latency variation in current high-speed designs may be relevant to proper operation and/or specification compliance. Although some variation may be unavoidable, it would still be desirable and useful to provide a reduction in latency variation across clock domain boundaries.